The “Boundary-Scan” testing system, also known as “JTAG” , is a testing technique in electronic systems for integrated circuits or chips (microprocessors, microcontrollers, memories, chipsets,etc.) To do this, they must be compatible with this system in order to be able to verify their electrical interconnects which, due to their encapsulated format, are not physically accessible for traditional testing systems. In this way, the testing or debugging times are reduced and reliability is also increased.
In 1985, a committee comprising professionals from several electronics companies formed the “Joint Test Action Group” or JTAG, with the aim of developing an alternative testing method that could eliminate or minimise as much as possible the limitations of the “In-Circuit” or ICT tests in new SMD designs.
In 1990, the Institute of Electrical and Electronics Engineers (IEEE) encoded it in the IEEE 1149.1-1990 standard titled “Standard Test Access Port and Boundary-Scan Architecture”.
The Boundary-Scan test basically consists of accessing the input/output or I/O interconnects of the chip through serial communication, normally with an adapter for PC, either to read its state or even to change it. Thus, we can check whether a certain input is in a state that does not correspond to it, or when forcing another output whether there is a change in one or several other outputs indicating the presence of a short circuit or even of several short circuits.
We can also detect an open circuit or a bad solder joint by checking whether an input does not change its state when it should by forcing the change in a specific output.
In order to use Boundary-Scan to test several chips, they are normally placed in cascade or chained in such a way that the first chip that communicates with the Boundary-Scan adapter for PC is also connected to the second chip, this second chip is connected to a third chip and so on, up to the last chip which will also be connected to the PC adapter to get the data from all the chips.
Another of the advantages of the Boundary-Scan is that it makes it possible to check other devices or chips that are not Boundary-Scan compatible, Such as for example RAM memory. If we focus on this case, if the memory is connected to a microprocessor that is Boundary-Scan compatible, when the I/O pins of the microprocessor are changed and read it is possible to access the RAM memory and read and write data to it, this checking its operation.
In addition, like with the previous example with RAM memory, it is also possible to read, write or program other devices such as FLASH memory, microcontrollers, etc., thus avoiding the need to have a specific programmer for such devices.
Communication with the Boundary-Scan device is normally done with an adapter that is connected to a PC and to the electronic circuit that has been equipped with a special connector for the Boundary-Scan test. The PC executes a program or testing software which detects the connected Boundary-Scan device or devices, and can read and change the state of inputs and outputs, execute testing sequences and even programme other devices that are not Boundary-Scan compatible, etc.
This testing system is a tool that IKOR has been applying for many years. We use it at the design stage and offer it to our customers in the industrialisation of our products with the aim of reducing testing times, reducing costs and of increasing the reliability of the electronic systems with respect to the ICT systems. In some cases, the Boundary-Scan is used as a support to even improve the reliability of an X-ray inspection, a resource that IKOR has available and which enables the checking of inaccessible and invisible interconnects.